As demand for greater bandwidth and data throughput increases, so too does the demand placed on integrated circuits to accommodate the processing and transmission speeds needed to support increased data throughput. Such is particularly the case where semi-conductor integrated circuits are used within optical transmission systems. Because optical transmission systems can operate at speeds of 40 Gbits per second, semi-conductor integrated circuits must also be able to generate data streams at that rate in order to supply a constant supply of data to optical modulators. In other words, an optical modulation system that can modulate a signal to optically transmit at a 40 Gbit/Sec. rate must be supplied with a data stream of 40 Gbit/Sec. This requires that the underlying electronic components be capable of generating a 40 Gbit/Sec. data stream.
Proposed 40 Gbit/Sec. optical transmission schemes contemplate a complimentary metal-oxide semiconductor (“CMOS”) silicon pre-processor application-specific integrated circuit (“ASIC”) providing 4×10 Gbit/Sec. data channels to a bipolar or BiCMOS ASIC which then multiplexes the 4 channels together to create one 40 Gbit/Sec. stream of data. This 40 Gbit/Sec. stream of data is then sent to an optical driver chain and ultimately appears as an optical signal on a fiber optic cable.
A problem with this scheme is that the 4×10 Gbit/Sec. data streams can become skewed with respect to one another between the CMOS preprocessing ASIC and the 40 Gbit/Sec. multiplexing ASIC. In other words, for a given bit, e.g., bit 0, that bit in each of the data streams does not arrive at the 40 Gbit/Sec. multiplexing ASIC at the same time. The result is that the bits become jumbled and out of sequence when they are multiplexed, thereby throwing the streams out of byte alignment. In addition, if the timing at the input ports of the 40 Gbit/Sec. multiplexing ASIC is not correct for all 4 10 Gbit/Sec. channels, the data within each individual data stream can be corrupted as well. This problem results in the individual data streams being out of bit alignment. As such, for the 40 Gbit/Sec. multiplexing ASIC to work correctly, it must be able to sample the 4×10 Gbit/Sec. data channels for which the bit alignment may be more than 50% out of alignment and for which the word alignment may also be out of sync.
Proposals have been made to solve this problem. The first requires that the ASIC vendors provide a transmission port in which 4×10 Gbit/Sec. output streams are both bit and byte aligned. For this scheme to work, the package and track matching must be maintained to better than 20 picoseconds. However, current ASIC and field programmable gate array (“FPGA”) vendors do not provide full bit and byte alignment in their devices even at 2.5 Gbit/Sec., let alone 10 Gbits/Sec. In part, this is because current suppliers treat each transmission port as an independent port without regard to subsequent multiplexing. In addition, bus margining at 10 Gbit/Sec. is quite difficult leaving an overall small timing margin.
Another proposal involves using the 10 Gbit/Sec. independent transmit devices on the silicon preprocessor ASIC described above. The 40 Gbit/Sec. multiplexing ASIC must then have an interface capable of fully recovering bit and byte alignment from the incoming data. A proposal has been made to use 4×10 Gbit/Sec. data channels with a 5th 10 Gbit/Sec. data channel used to carry alignment data. This scheme has several drawbacks itself. As an initial matter, the scheme only works if the 40 Gbit/Sec. multiplexing ASIC is implemented in a BiCMOS technology such that the short macros that must be provisioned can be instantiated. This immediately limits the choice of semiconductor technology for the 40 Gbit/Sec. multiplexing ASIC and clock generation function to a fully bipolar technology. However, bipolar devices that are optimized for 40 Gbit/Sec. cannot be used. This arrangement also means that the BiCMOS device has to make a 10 Gbit/Sec. serializer/deserializer (“SERDES”) link available in order to build the short port. For the most part, the CMOS device suppliers are only making 10 Gbit/Sec. links available in either 65 nanometer (“nm”) or 45 nm CMOS-only technologies. SERDES devices are high speed devices used to convert parallel data to a serial data stream and vice versa and can be stand alone devices or incorporated in ASIC. However, in the case of prior art devices, a SERDES device in the ASIC may have only limited availability. In addition, SERDES devices are not simple to build. Also, if indium phosphide (“InP”) technology or a gallium arsenide (“GaAs”) process in which flip-flops are implemented in order to combine the 40 Gbit/Sec. multiplexing function with the modulator driver function is used, then the aforementioned SERDES devices cannot be implemented. Thus the second proposed solution seriously limits semiconductor technology selection.
In order to function in known operating environments, the aforementioned SERDES device can not operate at 10 Gbit/Sec. and must demultiplex the incoming 10 Gbit/Sec. data streams down to 340 Mbit/Sec. or 170 Mbit/Sec. in order to process the data and correct byte alignment. The 40 Gbit/Sec. multiplexing ASIC must then first remultiplex each data stream back up to 10 Gbit/Sec. and then to 40 Gbit/Sec. This represents a significant increase in power for the 40 Gbit/Sec. multiplexing ASIC. Multiple power supply levels must also be supported in such a case.
Both of the above schemes imply that the two alignments which must be achieved, namely detailed bit alignment to allow correct sampling of incoming bits, and byte alignment must be solved within the 40 Gbit/Sec. multiplexing ASIC. This assumption impairs technology choices, technology availability, and increases power and complexity. It is therefore desirable to have a method and system for a high speed multiplexing system, such as a 40 Gbit/Sec. multiplexing system, that preserves bit and byte alignment among the multiplexed data streams and which minimizes power consumption while allowing transmission system designers flexibility in the technology underlying the semiconductor devices that implement the multiplexing system.